// *********************************************************************************
// Project Name : zkx2024
// Author       : xfsong
// Email        : 1293993416@qq.com
// Create Time  : 2024-04-16
// File Name    : rtl of module "inter_mem_cac"
// Module Name  :
// Called By    :
// Abstract     :
//
// 
// *********************************************************************************
// Modification History:
// Date         By              Version                 Change Description
// -----------------------------------------------------------------------
// 2024-04-25    xfsong          1.0                    integrate one dsp and four cacs in top 
// *********************************************************************************

module inter_mem_cac_top(
    input CLK, RST_N,
    st_cac_bus.cac  imc_ports,

    st_imc_bus.imc  i00_cac0_ports,
    st_imc_bus.imc  i01_cac1_ports,
    st_imc_bus.imc  i02_cac2_ports,
    st_imc_bus.imc  i03_cac3_ports

);
parameter FIX_ADDR = 4'd0;     //please set a 4-bit number from 0~15;
parameter INT_PRIO = 3'd0;     //please set a 3-bit number from 0~7;

wire full_cac0;
wire empty_cac0;
wire full_cac1;
wire empty_cac1;
wire full_cac2;
wire empty_cac2;
wire full_cac3;
wire empty_cac3;


dsp_cac_bus     dsp_fix_cac0_bus();
dsp_cac_bus     dsp_share_cac1_bus();
dsp_cac_bus     dsp_share_cac2_bus();
dsp_cac_bus     dsp_share_cac3_bus();

dsp#(
    .FIX_ADDR(FIX_ADDR)
)u_dsp(
    .CLK     (CLK),
    .RST_N   (RST_N),
    .SRAM_VLD_I (imc_ports.SRAM_VLD),
    .SRAM_SHARE_I(imc_ports.SRAM_SHARE),
    .SRAM_RELEASE_VLD_I(imc_ports.SRAM_RELEASE_VLD),
    .SRAM_RELEASE_I(imc_ports.SRAM_RELEASE),
    .RD_DATA_VLD(imc_ports.RD_DATA_VLD),
    .RD_DATA_VALUE(imc_ports.RD_DATA_VALUE),

    .i00_imc_ports(i00_cac0_ports),
    .i01_imc_ports(i01_cac1_ports),
    .i02_imc_ports(i02_cac2_ports),
    .i03_imc_ports(i03_cac3_ports),

    .i0_dsp_ports(dsp_fix_cac0_bus.dsp_ports), //in this bus sram_share is not used, caution!
    .i1_dsp_ports(dsp_share_cac1_bus.dsp_ports),
    .i2_dsp_ports(dsp_share_cac2_bus.dsp_ports),
    .i3_dsp_ports(dsp_share_cac3_bus.dsp_ports)

);

fix_cac#(
    .INT_PRIO_ADDR(INT_PRIO)
)u_fix_cac(
   .CLK     (CLK),
   .RST_N   (RST_N),
   .fix_cac_ports(dsp_fix_cac0_bus.cac_ports),
   .FULL_CAC(full_cac0),
   .EMPTY_CAC(empty_cac0)
);

share_cac#(
    .INT_PRIO_ADDR(INT_PRIO)
) u_share_cac1(
    .CLK    (CLK),
    .RST_N  (RST_N),
    .share_cac_ports (dsp_share_cac1_bus.cac_ports),
    .FULL_CAC(full_cac1),
    .EMPTY_CAC(empty_cac1)
);

share_cac#(
    .INT_PRIO_ADDR(INT_PRIO)
) u_share_cac2(
    .CLK    (CLK),
    .RST_N  (RST_N),
    .share_cac_ports (dsp_share_cac2_bus.cac_ports),
    .FULL_CAC(full_cac2),
    .EMPTY_CAC(empty_cac2)
);

share_cac#(
    .INT_PRIO_ADDR(INT_PRIO)
) u_share_cac3(
    .CLK    (CLK),
    .RST_N  (RST_N),
    .share_cac_ports (dsp_share_cac3_bus.cac_ports),
    .FULL_CAC(full_cac3),
    .EMPTY_CAC(empty_cac3)
);

assign imc_ports.EMPTY = {empty_cac3,empty_cac2,empty_cac1,empty_cac0};
assign imc_ports.FULL = {full_cac3,full_cac2,full_cac1,full_cac0};
//assign imc_ports.FULL = {empty_cac3,empty_cac2,empty_cac1,empty_cac0};
//assign imc_ports.EMPTY = {full_cac3,full_cac2,full_cac1,full_cac0};


endmodule


